1. Technical Field of the Present Invention
The present invention generally relates to analog to digital converters, and more specifically, to methods and apparatuses for testing the analog to digital converters for errors.
2. Background of the Present Invention
In the world of semiconductors, the Analog to Digital Converter (ADC) plays the ever increasing and important role of converting analog data to a digital format for interpretation by digital circuitry. The speed with which these ADCs must convert the analog data has been increasing exponentially over the past several years. The use of ADCs at high speeds typically also requires very accurate results. It is this combination of high speed with very accurate results that causes various timing related problems from sources such as metastability-induced errors. In general, a metastability state refers to the state of a circuit where it hangs internally between a high and low state and is unable to make a strong decision on its state until some period of time has passed.
FIG. 1 represents a simplified block diagram of a conventional high speed n-bit flash ADC 100. The ADC 100 includes a bank of 2nxe2x88x921 clocked comparators (Flash 104), Latches 116, and Pipelined encoding logic 114. The Flash 104 receives an analog signal and the bank of comparators (each comparing a differing voltage) produces a digital output to the Latches 116. In this example, the ADC 100 must deliver an n-bit encoded output with every clock cycle, and is therefore, pipelined (Pipelined encoding logic 114) to assist performance at high speeds.
As illustrated in FIG. 1, various clocks (clk1-4) are required for the various timing interfaces. The timing relationship between these clocks is difficult to design and simulate, and if not well aligned under all process and environment conditions will result in erroneous output codes. For example, if one of the comparators in Flash 104 has an input signal which is very close to its reference voltage, the comparator can enter a metastable state. Effects from the delay associated with this state can ripple through the encoding logic and, in the end, produce an incorrect ADC output code. Metastability problems are not limited to the comparators but can also occur in the Latches 116.
The Latches 116 that are used to capture the results provided by the comparators can also enter into a metastability state, independent of the comparators, with similar results. Of course, there are various ways in which the rate of metastability can be reduced or partially masked, but these never totally eliminate the occurrence.
Another kind of timing related problem for the ADC is similar to that seen in the digital logic domain, and depends on the data setup and hold times into the Latches 116. If the data is not held in a valid state during the critical window of time that the latch is being clocked, an error will occur. Verifying in simulation that the ADC is timed correctly is more difficult than in standard digital logic because the timing analysis tools must bridge the gap between digital and analog simulations.
There are several prior art methods used for testing the accuracy of an ADC. However, these methods fail to detect or reliably detect infrequently occurring errors.
It would, therefore, be a distinct advantage to have a method and system that could test the accuracy of an ADC and detect infrequently occurring errors. The present invention provides such a method and system.
The present invention is method and apparatus for testing ADC circuitry. More specifically, the present invention detects infrequently occurring errors by providing a series of waveforms to the ADC that have different amplitude, frequency, or voltage offset from one another. The outputs of the ADC for the waveforms are then analyzed for timing related errors.